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W83194BR-903 & W83194BG-903 STEPLESS VIA PT/PM MAIN CLOCK GENERATOR
Date:
5/2/2006
Revision: 1.0
W83194BR-903/W83194BG-903
W83194BR-903 Datasheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 4 5 6 7 8 9 1 0
n.a. n.a. 6 7,9,19 09/07/03 10/28/03 12/18/03 05/02/06 0.5 0.6 0.7 1.0
n.a. n.a. n.a. n.a. 1.0
All of the versions before 0.50 are for internal use. First published preliminary version. Modify frequency table Correction IC version, correction description and default value Update on Web and add lead free part some
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION .............................................................................................................. 1 PRODUCT FEATURES................................................................................................................... 1 PIN CONFIGURATION.................................................................................................................... 2 BLOCK DIAGRAM........................................................................................................................... 2 PIN DESCRIPTION ......................................................................................................................... 3 5.1 Crystal I/O...........................................................................................................................................3 5.2 CPU, AGP, and PCI Clock Outputs...................................................................................................3 5.3 Fixed Frequency Outputs...................................................................................................................4 5.4 I2C Control Interface...........................................................................................................................4 5.5 Power Management Pins...................................................................................................................5 5.6 IREF selects Function........................................................................................................................5 5.7 Power Pins .........................................................................................................................................5 6. 7. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE..................................................... 6 I2C CONTROL AND STATUS REGISTERS.................................................................................... 7 7.1 Register 0: Frequency Select (Default = 10h)...................................................................................7 7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)....................................................7 7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)......................................................8 7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)............................................8 7.5 Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable, 0 = Stopped) (Default: BFh)..8 7.6 Register 5: Watchdog Control (Default: 02h) ....................................................................................9 7.7 Register 6: Reserved (Default: 50h) (Read Only) .............................................................................9 7.8 Register 7: Winbond Chip ID (Default: 70h) (Read Only)...............................................................10 7.9 Register 8: M/N Program (Default: 90h)..........................................................................................10 7.10 Register 9: M/N Program (Default: 7Ah) .........................................................................................10 7.11 Register 10: M/N Program (Default: BBh).......................................................................................11 7.12 Register 11: Spread Spectrum Programming (Default: 0Bh) .........................................................11 7.13 Register 12: Divisor and Step-less Enable Control (Default: FBh).................................................11 7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh) .................................................12 7.15 Register 14: Control (Default: 0Ah)..................................................................................................12 7.16 Register 15: SST & Skew Control (Default: 2Ch) ...........................................................................13 7.17 Register 16: Skew Control (Default: 24h)........................................................................................13 7.18 Register 17: Slew rate Control (Default: 00h)..................................................................................13 7.19 Register 18: Slew rate Control (Default: 00h)..................................................................................14 7.20 Register 19: Slew rate Control (Default: D2h).................................................................................14 - II -
W83194BR-903/W83194BG-903
7.21 Register 20: Watch dog timer (Default: 08h)...................................................................................14 7.22 Register21: Fix Mode Control (Default: 00h)...................................................................................15 8. ACCESS INTERFACE................................................................................................................... 16 8.1 Block Write protocol .........................................................................................................................16 8.2 Block Read protocol .........................................................................................................................16 8.3 Byte Write protocol ...........................................................................................................................16 8.4 Byte Read protocol...........................................................................................................................16 9. SPECIFICATIONS......................................................................................................................... 17 9.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................17 9.2 General Operating Characteristics ..................................................................................................17 9.3 Skew Group timing clock .................................................................................................................18 9.4 CPU 0.7V Electrical Characteristics ................................................................................................18 9.5 AGP Electrical Characteristics.........................................................................................................18 9.6 PCI Electrical Characteristics...........................................................................................................19 9.7 24M, 48M Electrical Characteristics ................................................................................................19 9.8 REF Electrical Characteristics .........................................................................................................19 10. ORDERING INFORMATION ......................................................................................................... 20 11. HOW TO READ THE TOP MARKING .......................................................................................... 20 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................. 21
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
1. GENERAL DESCRIPTION
The W83194BR-903 is a Clock Synthesizer for VIA PT880/PM880 chipset. W83194BR-903 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and AGP clocks setting, support two 25MHz clock outputs, all clocks are externally selectable with smooth transitions. The W83194BR-903 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-903 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-903 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * * * 3 0.7V current-mode Differential pairs clock outputs 2 2.5V 25MHz clock outputs 3 AGP clock outputs 10 PCI synchronous clocks 1 24_48Mhz clock output for super I/O. 1 48 MHz clock output for USB. 2 14.318MHz REF clock outputs. AGP/PCI clock out supports synchronous and asynchronous mode Smooth frequency switch with selections from 100 to 400MHz Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Programmable clock outputs Slew rate control and Skew control Watch Dog Timer and RESET# output pins
* 48-pin SSOP package
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
3. PIN CONFIGURATION
FS1* /REF0 FS0 & /REF1 VDDREF XIN XOUT GND FS2 & /PCI_F0 FS4 & /PCI_F1 PCI_F2 VDDPCI GND MODE & /PCI0 PCI1 PCI2 PCI3 PCI4 VDDPCI GND PCI_STOP#*/PCI5 CPU_STOP#*/PCI6 FS3 & /48MHz SEL24_48# & /24_48MHz GND VDD48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GND IREF CPUT_ITP CPUC_ITP GND CPUT1 CPUC1 VDDCPU CPUT0 CPUC0 GND 25MHz_0 25MHz_1 VDD2.5 VTT_PWRGD/PD#* SDATA* SCLK* RESET# AGP_0 GND VDDAGP AGP_1 AGP_2
#: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
PLL2
Divider
48MHz 24_48MHz 2
XN I XU OT
XA TL OC S
REF 0:1
PLL1 Spread Spectrum
VCOCLK
2 2
CPUT0:1 CPUC0:1 CPUT_ITP CPUC_ITP
M/N/Ratio RM O
2
Divider
3
25MHz_0:1 AGP0:2
VTT_PWRGD FS(0:4) MODE & SEL24_48# &
Latch &O PR
1 0
PCI_F0:2,PC I_0:6
PD#* PCI_STOP#* CPU_STOP#*
Control Logic &Config Register IREF
RESET#
Rref
S AA DT* SCLK*
I2C Interface
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W83194BR-903/W83194BG-903
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT OD I/OD # * &
Input Latched input at power up, internal 120k pull up. Latched input at power up, internal 120k pull down. Output Open Drain Bi-directional Pin, Open Drain. Active Low Internal 120k pull-up Internal 120 k pull-down
5.1
Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
4 5
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF).
5.2
CPU, AGP, and PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
42,39,41,38 CPUT [0:1] CPUC [0:1] 45,44 29,26,25 7 CPUT_ITP, CPUC_ITP AGP0: 2 PCI_F0 FS2 8
&
OUT OUT OUT OUT
Low skew (< 250ps) differential clock outputs for host frequencies of CPU Differential clock outputs for host frequencies of CPU 3.3V AGP clock outputs. 3.3V PCI free running clock output.
INtd120k Latched input for FS2 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. OUT 3.3V PCI free running clock output. INtd120k Latched input for FS4 at initial power up for H/W selecting the output frequency, This is internal 120K pull down. OUT
&
PCI_F1 FS4
&
12
PCI0 MODE
3.3V PCI clock output.
INtd120k Latched input for pin 19,20 at initial power up selecting the 0=PCI5, PCI6 clock output, 1=PCI_STOP and CPU _STOP control pin. This is internal 120K pull down.
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
CPU, AGP, and PCI Clock Outputs, continued.
PIN
PIN NAME
TYPE
DESCRIPTION
9 19
PCI_F2 PCI5 PCI_STOP#*
OUT OUT
3.3V PCI free running clock output. 3.3V PCI clock output. Select by pin 12 MODE& power up initial =0.
INtp120k Active low, Stop all PCI clock output besides the free running clocks. Select by pin 12 MODE& power up initial =1. OUT 3.3V PCI clock output. Select by pin 12 MODE& power up initial =0.
20
PCI6 CPU_STOP#*
INtp120k Active low, Stop all CPU clock outputs. Select by pin 12 MODE& power up initial =1. OUT Low skew (< 250ps) PCI clock outputs.
13,14,15,16 PCI [1:4]
5.3
Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
1
REF0 FS1*
OUT INtp120k OUT INtd120k OUT INtd120k OUT
14.318MHz output. Latched input for FS1 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. 14.318MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 48MHz clock output for USB. Latched input for FS3 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 24MHz or 48MHz(default) clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 5 bit 7. Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 48MHz. In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 5 bit 7. 25MHz 2.5V push pull clock output.
2
REF1 FS0& 48MHz FS3& 24_48MHz
21
22
SEL24_48#&
INtd120k
36,35
25MHz_[0:1]
OUT
5.4
I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
32 31
SDATA* SCLK*
I/OD INtp120k
Serial data of I C 2-wire control interface with internal 120K pull-up resistor. Serial clock of I2C 2-wire control interface with internal 120K pull-up resistor.
2
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W83194BR-903/W83194BG-903
5.5 Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
33
VTT_PWRGD PD#*
46 30
IREF
RESET#
Power good input signal is power on trapping with HIGH active. This 3.3V input is level sensitive strobe used to determine FS [4:0]. This pin is HIGH active. INtp120k Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up OUT Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. OD System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout.
IN
5.6
IREF selects Function
BOARD TARGET TRACE/TERM Z REFERENCE R, IREF = ADD/(3*RR) OUTPUT CURRENT VOH @ Z
50 50
Rr =221 1% IREF = 5.00mA Rr =475 1% IREF = 2.32mA
Ioh=4*IREF Ioh=6*IREF
1.0V @ 50 0.7V @ 50
5.7
Power Pins
PIN PIN NAME TYPE DESCRIPTION
3 10,17 27 40 24 34 48 6,11,18,23,28, 37,43,47
VDDREF VDDPCI VDDAGP VDDCPU VDD48 VDD2.5 VDDA GND
PWR PWR PWR PWR PWR PWR PWR PWR
3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for AGP. 3.3V power supply for CPU. 3.3 power supply for 48MHz. 2.5V power supply for 25MHz. 3.3V power for Analog power Ground pin
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3).
FS4 FS3 FS2 FS1 FS0 CPU (MHZ) 3V66 (MHZ) PCI (MHZ)
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1
0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0
0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0
100.00 200.01 133.34 200.01 400.01 266.68 101.1 202.2 134.68 100.00 200.01 133.34 200.01 400.01 266.68 105.04 210.07 140.05
66.67 66.67 66.67 66.67 66.67 66.67 67.34 67.34 67.34 66.67 66.67 66.67 66.67 66.67 66.67 70.02 70.02 70.02
33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.33 33.33 33.33 33.33 33.33 33.33 35.01 35.01 35.01
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W83194BR-903/W83194BG-903
7. I2C CONTROL AND STATUS REGISTERS
7.1
BIT
Register 0: Frequency Select (Default = 10h)
NAME PWD DESCRIPTION
7 6 5 4 3 2
SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL
0 0 0 1 0 0
Frequency selection by software via I2C
Enable software program FS [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 3. Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum Enabled Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0.
1
EN_SPSP
0
0
EN_SAFE_FREQ
0
7.2
BIT
Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
45,44 42,41 39,38 -
1 1 1 X X X X X
CPUT_IPT/CPUC_IPT output control. CPUT1 / C1 output control. CPUT0 / C0 output control. Power on latched value of FS4 pin. Default: 0 (Read only) Power on latched value of FS3 pin. Default: 0 (Read only) Power on latched value of FS2 pin. Default: 0 (Read only) Power on latched value of FS1 pin. Default: 1 (Read only) Power on latched value of FS0 pin. Default: 0 (Read only)
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
7.3
BIT
Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
9 8 7 Reserve 20 19 16 15
1 1 1 1 1 1 1 1
PCI_F2 output control. PCI_F1 output control. PCI_F0 output control. Reserved PCI6 output control. PCI5 output control. PCI4 output control. PCI3 output control.
7.4
BIT
Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
14 13 12 25 26 29 -
1 1 1 1 1 1 1 1
PCI2 output control. PCI1 output control. PCI0 output control. Don't modify it AGP_2 output control. AGP_1 output control. AGP_0 output control. Don't modify it
7.5
BIT
Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable, 0 = Stopped) (Default: BFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
22 21 2 1 35 36
1 0 1 1 1 1 1 1
24_48MHz output control. Reserved 48MHz output control. Reserved REF1 output control. REF0 output control. 25MHz_1 output control. 25MHz_0 output control.
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W83194BR-903/W83194BG-903
7.6
BIT
Register 5: Watchdog Control (Default: 02h)
NAME PWD DESCRIPTION
7 6
SEL24_48 EN_WD
X 0
24 / 48 MHz output selection, 1: 24 MHz.0: 48 MHz. (Default) Default value follow hardware trapping data on SEL24_48# pin. Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0.
5
WD_TIMEOUT
0
Read Back only, Timeout Flag, This bit is Read Only. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting.
4 3 2 1 0
SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 1 0 These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1.
7.7
BIT
Register 6: Reserved (Default: 50h) (Read Only)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 1 0 1 0 0 0 0
Reserved Reserved Reserved Reserved
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
7.8
BIT
Register 7: Winbond Chip ID (Default: 70h) (Read Only)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0 1 1 1 0 0 0 0
Winbond Chip ID. W83194BR-903 (SA5870) Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
7.9
BIT
Register 8: M/N Program (Default: 90h)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] M_DIV [6] M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 0 1 0 0 0 0
Programmable N divisor value. Bit 7 ~0 are defined in the Register 9. Programmable M divisor value.
7.10 Register 9: M/N Program (Default: 7Ah)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0 1 1 1 1 0 1 0 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 8.
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W83194BR-903/W83194BG-903
7.11 Register 10: M/N Program (Default: BBh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [9] N3<6> N3<5> N3<4> N3<3> N3<2> N3<1> N3<0>
1 0 1 1 1 0 1 1
Programmable N divisor bit 9. Programmable N3 divisor bit 6 ~0 for programmable 25M clocks. M3=10000 (Fix) Frequency range: 21.7M ~ 28.8M Resolution: 56K
7.12 Register 11: Spread Spectrum Programming (Default: 0Bh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 0 1 0 1 1
Spread Spectrum Up Counter bit 3 ~ bit 0.
Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000
7.13 Register 12: Divisor and Step-less Enable Control (Default: FBh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved DS9 DS5 Reserved Reserved DS2 DS1 DS0
1 1 1 1 1 0 1 1
Reserved Define the AGP divider ratio Table-2 integrate the all divider configuration Reserved Define the CPU divider ratio Refer to Table-2
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
Table-2 CPU, AGP, PCI divider ratio selection Table LSB MSB Bit2/ Bit9 0 1 0 Div6 Div10 AGP Bit5 1 Div7 Div12 00 Div2 Div8 01 Div3 Div8 CPU Bit1, 0 10 Div4 Div8 11 Div6 Div8
7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh)
BIT NAME PWD DESCRIPTION
7 EN_MN_PROG
0
6 5 4 3 2 1 0
Reserved Reserved Reserved IVAL<3> IVAL<2> IVAL<1> IVAL<0>
0 0 0 1 1 1 1
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<4:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). Reserved Reserved Reserved Charge pump current selection
7.15 Register 14: Control (Default: 0Ah)
BIT NAME PWD DESCRIPTION
7
CPUT_DRI
0
6 5 4 3 2 1 0
Reserved SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0]
0 0 0 1 0 1 0
CPUT output state in during POWER DOWN or Stop mode assertion. 1: Driven (2*Iref), 0: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. Reserved Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us
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W83194BR-903/W83194BG-903
7.16 Register 15: SST & Skew Control (Default: 2Ch)
BIT NAME PWD DESCRIPTION
7 6 5 4 3
INV_CPU Reserved SPSP_TYPE SPSP1 SPSP0
0 0 1 0 1
2 1 0
ASKEW [2] ASKEW [1] ASKEW [0]
1 0 0
Invert the CPU phase, 0: Default, 1: Inverse Reserved Spread spectrum implementation method 1: Pendulum type, 0: Original Spread Spectrum type select. 00: Down 1% 01: Down 0.5% 10: Center +/- 0.5% 11: Center +/- 0.25% CPU to AGP skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_AGP_SKEW [2:0] setting
7.17 Register 16: Skew Control (Default: 24h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
INV_AGP INV_PCI Reserved Reserved Reserved PSKEW [2] PSKEW [1] PSKEW [0]
0 0 1 0 0 1 0 0
Invert the AGP phase, 0: Default, 1: Inverse Invert the PCI phase, 0: Default, 1: Inverse Reserved
CPU to PCI skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_PCI_SKEW [2:0] setting
7.18 Register 17: Slew rate Control (Default: 00h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_F2_S2 PCI_F2_S1 PCI_F0_S2 PCI_F0_S1 AGP_2_S2 AGP_2_S1 AGP_10_S2 AGP_10_S1
0 0 0 0 0 0 0 0
PCI_F2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI_F1 / PCI_F0 slew rate control 11: Strong, 00: Weak, 10/01: Normal AGP2 slew rate control 11: Strong, 00: Weak, 10/01: Normal AGP_1 /AGP_0 slew rate control 11: Strong, 00: Weak, 10/01: Normal
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
7.19 Register 18: Slew rate Control (Default: 00h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_65_S2 PCI_65_S1 PCI_42_S2 PCI_42_S1 PCI_10_S2 PCI_10_S1 REF_S2 REF_S1
0 0 0 0 0 0 0 0
PCI6, 5 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI4, 3,2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF0, 1 slew rate control 11: Strong, 00: Weak, 10/01: Normal
7.20 Register 19: Slew rate Control (Default: D2h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU1STOP_EN CPU0STOP_EN 25MHz_S2 25MHz_S1 INV_48MHz 48MHz_S2 48MHz_S1 MODE
1 1 0 1 0 0 1 X
Stop CPU1 clocks, 1: Enable stop feature, 0: Disable Stop CPU0 clocks, 1: Enable stop feature, 0: Disable 25MHz_1,0 slew rate control 11: Strong, 00: Weak, 10/01: Normal Invert the 48MHz phase, 0: In phase with 24_48MHz 1: 180 degrees out of phase 48MHz/24_48MHz slew rate control 11: Strong, 00: Weak, 10/01: Normal Pin 19,20 Mode selection 1: PCI_STOP, CPU_STOP Control pin 0: PCI5, PCI6 (Default) Default value follow hardware trapping data on MODE&/PCI0 pin.
7.21 Register 20: Watch dog timer (Default: 08h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SRCF1 WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0]
0 0 0 0 1 0 0 0
SRC frequency select, 00/01: 25MHz(Default), 10: 100mhZ, 11: 200MHz Setting the down count depth. One bit resolution represents 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value
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W83194BR-903/W83194BG-903
7.22 Register21: Fix Mode Control (Default: 00h)
BIT NAME PWD DESCRIPTION
7 6 5 4
Tri-state Reserved Reserved FIX_SEL
0 0 0 0
Tri-state all output if set 1 Don't modify it Don't modify it AGP output frequency select mode 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency Reg21 bit 0~2
3 2 1 0
SRCF0 ASEL_2 ASEL_1 ASEL_0
0 0 0 0
SRC frequency select Asynchronous AGP/PCI frequency table selection ASEL_<2:0> 001: 66 / 33M 011: 88 / 44M 101: 66 / 33M 111: 88 / 33M 010: 75.43 / 37.7M 100: 88 / 44M 110: 75.43 / 33M 000: Clock from PLL1
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
8. ACCESS INTERFACE
The W83194BR-903 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-903 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8'h00
8.3
Byte Write protocol
8.4
Byte Read protocol
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W83194BR-903/W83194BG-903
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model)
-0.5V to +4.6V - 0.5 V to + 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2
General Operating Characteristics
PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS
VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI= 3.3V 5 %, TA = 0C to +70C, Cl=10pF Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 0.8 Vdc Vdc Vdc Vdc mA pF pF nH All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 400 MHz PCI = 33.3 Mhz with load
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
9.3 Skew Group timing clock
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI = 3.3V 5 %, TA = 0C to +70C, Cl=10pF AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew 1.5 2.6 3.5 200 250 500 1000 500 ns ps ps ps ps ps Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
9.4
CPU 0.7V Electrical Characteristics
VDDA=VDDCPU= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=475, IREF=2.32mA, Ioh=6*IREF
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time Fall Time Absolute Voltages Duty Cycle crossing point
175 175 250
700 700 550 150
ps ps mV ps %
100 to 200 Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz
Cycle to Cycle jitter 45
55
9.5
AGP Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
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W83194BR-903/W83194BG-903
9.6 PCI Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDPCI= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
9.7
24M, 48M Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 500 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
9.8
REF Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDREF= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 1000 1000 4000 4000 1000 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194BR-903 W83194BG-903
48 PIN SSOP 48 PIN SSOP (Lead free part)
Commercial, 0C to +70C Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83194BR-903 28051234 342GAASA W83194BG-903 28051234 342GAASA
1st line: Winbond logo and the type number: Normal:W83194BR-903, Lead free part:W83194BG-903 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G A A SA 320: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: Internal use code All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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W83194BR-903/W83194BG-903
12. PACKAGE DRAWING AND DIMENSIONS
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Publication Release Date: May 2006 Revision 1.0
W83194BR-903/W83194BG-903
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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